In a semiconductor test system, a conventional I/O pin electronics circuit has an I/O common pin which functions both as a driver (DR) and a comparator (CP) as shown in FIG. 5(a). The DR and the CP are connected to a device to be tested (DUT) through a cable having a signal propagation delay time T.
FIG. 5(b) shows a timing diagram of a case where writing and reading operations are repeated. The output data DR1 from the DR reaches the DUT terminal after a time T, which becomes writing data W1. When the reading operation begins, the data R read out from the DUT reaches the CP terminal after the time T. At the end of the reading operation, in order to immediately begin the writing operation, data DR2 must be generated by the DR by the time T earlier than the time when writing data W2 reaches the DUT. The data DR2 generated by the DR reaches the CP terminal without delay. As a result, at the CP terminal, there exists a time in which the reading data R from the DUT and the data DR2 generated by the DR itself are combined. The time during which such signal coupling occurs is twice the length of the time T in which accurate comparison and evaluation of the DUT is unavailable. This time range is called an I/O dead band, and is determined by the signal propagation delay time T between the DR, the CP and the DUT.
When testing high speed devices wherein the I/O dead band poses a problem, an I/O separate test is performed in which a signal path from the DR to the DUT and a signal path from the DUT to the CP are separated from one another for testing the device as shown in FIG. 6(a). As shown in FIG. 6(b), signal coupling will not be involved at the CP terminal between the reading data R from the DUT and the output data DR1 and DR2 from the DR. Hence, the accurate comparison and evaluation of the device can be performed by the CP. The output data DR2 and the read data R from the DUT will be coupled at the DR terminal. However, the coupling between the traveling waves only pass each other with no adverse effects, and the wave form from the DUT will not affect the CP terminal since it is terminated by the DR terminal.
In general, an I/O pin electronics circuit utilizes an I/O common pin. FIG. 7 shows a conventional example in which an I/O common pin is used for an I/O separate test wherein the DR and the DUT, and the DUT and the CP are respectively connected by separate routes. In this example, an I/O common pin CH1 is used as the DR and an I/O common pin CH2 is used as the CP.
An I/O separate pin as shown in FIG. 8 is suitable for the I/O separate test. The I/O separate test can be performed by connecting the DR and the DUT, and the DUT and the CP, separately.
As shown in FIG. 7, in case where the I/O separate test is performed by the I/O common pin, the number of the I/O common pins required is doubled compared to that required in the normal test situation using the I/O common pins. Hence, the number of DUTs that can be simultaneously tested is decreased in half. Further, the comparator circuits and comparison voltage generator circuits in the CH1 are useless in such a situation since the CH1 is used only as a driver DR. As for the CH2, wave formatter circuits and voltage generation circuits are useless since the CH2 is used only as a comparator CP.
As shown in FIG. 8, the I/O separate test by the I/O separate pin does not produce useless circuits in the comparator circuits, comparison voltage generation circuits, wave formatter circuits or voltage generation circuits. However, the I/O separate pin cannot perform the test as an I/O common pin.
In the I/O separate test, for the reading cycle, the DUT has to have sufficient drive power since both of the DR and CP ends are terminated. The DUT having insufficient drive power cannot undertake the I/O separate test, and has to undertake only the I/O common test. Further, in the I/O separate test, in testing one pin of the DUT by both the DR and the CP, the required number of wiring between the DUT and the semiconductor test system increases compared to the case of the I/O common test. When a plurality of DUTs are tested in parallel at the same time, the I/O common test is preferable to avoid the complexity of the wiring.